A lateral high-voltage NMOS transistor in which source, channel and drain are arranged alongside one another at the top side of a p-type substrate is known for example from U.S. Pat. No. 6,455,893 B1. A drain-side edge of the gate electrode is arranged on a field plate. The source and drain regions are n-conducting, and the drain region is arranged in a likewise n-conducting drain extension region, which continues as far as a drift path, which runs subsequently to the channel region below the field plate.
The publication by R. Zhu et al.: “Implementation of High-Side, High-Voltage RESURF LDMOS in a sub-half Micron Smart Power Technology” in Proceedings of 2001 International Symposium on Power Semiconductor Devices & ICs, Osaka, pp. 403-406, describes a high-voltage NMOS transistor in which a p-type body region with an n+-type source region and an n-type well with an n+-type drain region arranged therein are present. The p-type body region may be arranged in the n-type well or, in the case of a novel configuration by comparison therewith, in further p-conducting regions. A p-conducting channel region is controlled by means of a gate electrode drawn partly onto a field oxide arranged between the drain region and the channel region.
The publication by H. Lu and C. A. T. Salama: “A 2 GHz, 60 V-Class, SOI Power LDMOSFET for Base Station Applications” in International Symposium on Power Semiconductor Devices (ISPSD) 2003, pages 270-273, describes an LDD extension high-voltage component in which there is not a field oxide present between the drain region and the channel region, but rather an LDD region (lightly doped drain), which is n−-doped and adjoins the n+-doped drain region. This component is provided for radiofrequency applications.
U.S. Pat. No. 6,097,063 describes a high-voltage NMOS transistor in which a deep n-conductively doped well and therein a p-conductively doped well are formed in a weakly p-conductively doped substrate, an n-conductively doped source region, an n-conductively doped drain region and a channel region adjoining the source region and also a gate electrode, which is arranged above the channel region and is electrically insulated from the channel region, are present and a drift path is present between the channel region and the drain region. A portion of the drift path is formed by an n-conducting layer on the p-conductively doped well, which is produced by thermally oxidizing the p-conducting top side of the substrate. This exploits the fact that phosphorus ions distributed non-uniformly and boron ions that are resolved or distributed in the lattice are present there, which are distributed uniformly by the oxidation.
DE 199 29 235 A1 describes a vertical DMOS transistor which is insulated from adjoining components by insulating regions.
U.S. Pat. No. 5,438,215 describes a power MOSFET in which more highly doped regions of an opposite conduction type to the rest of the inner zone are arranged in the region of the space charge zone. Situated in between are zones which are of the conduction type of the inner zone but have a higher doping.
U.S. Pat. Nos. 6,812,524 and 6,756,636 describe high-voltage NMOS transistors in which p-type strips isolated from a deep p-conductively doped well are present in the drift zone.
U.S. Pat. No. 5,347,155 describes a power semiconductor component having a frame-type drain region.
U.S. Pat. No. 6,100,572 describes a power MOSFET having a shallow p-conductively doped well, into which the source region projects.
It is often desirable to use a high-voltage NMOS transistor instead of a high-voltage PMOS transistor. However, the high-voltage NMOS transistors likewise exhibit the problem that the operating properties and the electrical properties, in particular the non-reactive resistance in the on state, the capability of resisting so-called latch-up and the occurrence of a source-drain breakdown, cannot be optimized simultaneously. It is necessary, therefore, to make a certain compromise between these properties.